VERILOG

Welcome to the www.nammavlsi.com Interactive Verilog Tutorial.

Whether you are an experienced programmer or not, this website is intended for everyone who wishes to learn the Verilog programming language. Just click on the chapter you wish to begin from, and follow the instructions. Good luck! 

After you have a thorough understanding of digital design principles, we will explore the syntax and semantics of Verilog. You’ll discover how to write Verilog code effectively, exploring data types, operators, and modules. We will lead you through both structural and behavioral modeling styles, instructing you on how to describe the structure and behavior of digital circuits.

To enhance your learning, we will provide you with a variety of examples and exercises.

You will be taught how to simulate your Verilog designs, analyze their results, and verify their correctness and functionality. We will learn about various verification methods, including test benches, and provide guidance on how to validate your designs in an effective manner.

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Verilog Index:

INTRODUCTION TO VERILOG:

LANGUAGE CONSTRUCTS AND CONVENTIONS:

  • Introduction
  • Keywords
  • Identifiers
  • White Space Characters
  • Comments
  • Numbers
  • Strings
  • Logic Values
  • Strengths
  • Data Types
  • Scalars and Vectors
  • Parameters
  • Operators

GATE LEVEL MODELLING:

  • Introduction
  • AND Gate Primitive
  • Module Structure
  • Other Gate Primitives
  • Illustrative Examples
  • Tri-State Gates
  • Array of Instances of Primitives
  • Design of Flip-Flops with gate primitives
  • Delays
  • Strengths and Contention Resolution
  • Net Types
  • Design of Basic Circuits

MODELLING AT DATA FLOW LEVEL:

  • Introduction
  • Continuous Assignment Structures
  • Delays and Continuous Assignments
  • Assignment to Vectors
  • Operators

BEHAVIORAL MODELLING

  • Introduction
  • Operations and Assignments
  • Functional Bifurcation
  • 'Initial' Construct
  • 'Always' Construct
  • Examples
  • Assignments with Delays
  • 'Wait' Construct
  • Multiple Always Blocks
  • Designs at Behavioral Level
  • Blocking and Non-Blocking Assignments
  • The Case Statement
  • Simulation Flow
  • 'if' and 'if-else' constructs
  • 'assign -- de-assign' construct
  • 'repeat' construct
  • 'for' loop
  • the 'disable' construct
  • 'While' loop
  • 'forever' loop
  • Parallel blocks
  • 'force-release' construct
  • Event

SWITCH LEVEL MODELLING

  • Basic Transistor Switches
  • CMOS Switch
  • Bi-directional Gates
  • Time Delays with Switch Primitives
  • Instantiations with Strengths and Delays
  • Strength Contention with Trireg Nets

SYSTEM TASKS, FUNCTIONS AND COMPILER DIRECTIVES:

  • Parameters
  • Path delays
  • Module Parameters
  • System Tasks and Functions
  • File-Based Tasks and Functions
  • Compiler Directives
  • Hierarchical Directives
  • Hierarchical Access
  • User-Defined Primitives (UDP)

Verilog Designs with Testbenches

  • Half Adder
  • 1-bit Full Adder
  • 1-bit Full Adder using Half Adder
  • 4-bit Full adder using Half Adder
  • Mux using Case statement
  • Mux using logical expression
  • Mux using Conditional operator
  • ALU
  • D Flip-Flop with synchronous reset
  • D Flip-Flop with Asynchronous reset
  • Sequence Detector using Mealy machine (1101, Non-overlapping)
  • Sequence Detector using Moore machine (1101, Non-Overlapping)
  • Sequence Detector using Mealy machine (1101, Overlapping)
  • Sequence Detector using Moore machine (1101, Overlapping)
  • Count the Number of 1's
  • Binary to Gray Conversion
  • Up Down Counter
  • Random Counter
  • Clock Divider
  • PIPO
  • N-bit Universal Shift Register
  • 4 bit LSFR
  • Single port RAM (128x8)
  • Dual port RAM (128x8)
  • Synchronous FIFO
  • Asynchronous FIFO
  • 8x8 Sequential Multiplier
  • 64 bit Pipelined Multiplier
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